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?2015 integrated device technology, inc. 1 june 2015 dsc-5679/6 ? ce 0r r/ w r ce 1r be 0r be 1r be 2r be 3r 512k x 36 memory array address decoder a 18r a 0r address decoder ce 0l r/ w l ce 1l be 0l be 1l be 2l be 3l dout0-8_l dout9-17_l dout18-26_l dout27-35_l dout0-8_r dout9-17_r dout18-26_r dout27-35_r b e 0 l b e 1 l b e 2 l b e 3 l b e 3 r b e 2 r b e 1 r b e 0 r i/o 0l- i/o 35l a 18l a 0l i/o 0r - i/o 35r di n_l addr_l di n_r addr_r oe r oe l arbitration interrupt semaphore logic sem l int l (1) busy l r/ w l oe l r/ w r oe r ce 0l ce 1l ce 0r ce 1r busy r sem r int r (1) 5679 drw 01 zz control logic zz l (2) jtag tck trst tms tdi tdo zz r (2) functional block diagram full on-chip hardware support of semaphore signaling between ports fully asynchronous operation from either port separate byte controls for multiplexed bus and bus matching compatibility sleep mode inputs on both ports single 2.5v (100mv) power supply for core lvttl-compatible, selectable 3.3v (150mv)/2.5v (100mv) power supply for i/os and control signals on each port includes jtag functionality available in a 256-ball ball grid array industrial temperature range (?40c to +85c) is available for selected speeds green parts available, see ordering information features true dual-port memory cells which allow simultaneous access of the same memory location high-speed access ? commercial: 10/12/15ns (max.) ? industrial: 12ns (max.) rapidwrite mode simplifies high-speed consecutive write cycles dual chip enables allow for depth expansion without external logic idt70t653m easily expands data bus width to 72 bits or more using the busy input when cascading more than one device busy input for port contention management interrupt flags high-speed 2.5v 512k x 36 asynchronous dual-port static ram with 3.3v 0r 2.5v interface idt70t653m notes: 1. int is non-tri-state totem-pole outputs (push-pull). 2. the sleep mode pin shuts off all dynamic inputs, except jtag inputs, when asserted. optx, int x and the sleep mode pins themselves (zzx) are not affected during sleep mode.
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 2 description the idt70t653m is a high-speed 512k x 36 asynchronous dual- port static ram. the idt70t653m is designed to be used as a stand- alone 18874k-bit dual-port ram. this device provides two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature controlled by the chip enables (either ce 0 or ce 1 ) permit the on-chip circuitry of each port to enter a very low standby power mode. the idt70t653m has a rapidwrite mode which allows the designer to perform back-to-back write operations without pulsing the r/ w input each cycle. this is especially significant at the 10ns cycle time of the idt70t653m, easing design considerations at these high performance levels. the 70t653m can support an operating voltage of either 3.3v or 2.5v on one or both ports, controlled by the opt pins. the power supply for the core of the device (v dd ) is at 2.5v.
3 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges pin configuration (1,2,3) notes: 1. all v dd pins must be connected to 2.5v power supply. 2. all v ddq pins must be connected to appropriate power supply: 3.3v if opt pin for that port is set to v dd (2.5v), and 2.5v if opt pin for that port is set to v ss (0v). 3. all v ss pins must be connected to ground supply. 4. package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5. this package code is used to reference the package diagram. 70t653m bc bc-256 (4,5) 256-pin bga top view e16 i/o 14r d16 i/o 16r c16 i/o 16l b16 nc a16 nc a15 nc b15 i/o 17l c15 i/o 17r d15 i/o 15l e15 i/o 14l e14 i/o 13l d14 i/o 15r d13 v dd c12 a 6l c14 opt l b14 nc a14 a 0l a12 a 5l b12 a 4l c11 busy l d12 v ddqr d11 v ddqr c10 sem l b11 nc a11 int l d8 v ddqr c8 be 1l a9 ce 1l d9 v ddql c9 be 0l b9 ce 0l d10 v ddql c7 a 7l b8 be 3l a8 be 2l b13 a 1l a13 a 2l a10 oe l d7 v ddqr b7 a 9l a7 a 8l b6 a 12l c6 a 10l d6 v ddql a5 a 14l b5 a 15l c5 a 13l d5 v ddql a4 a 17l b4 a 18l c4 a 16l d4 v dd a3 nc b3 tdo c3 v ss d3 i/o 20l d2 i/o 19r c2 i/o 19l b2 nc a2 tdi a1 nc b1 i/o 18l c1 i/o 18r d1 i/o 20r e1 i/o 21r e2 i/o 21l e3 i/o 22l e4 v ddql f1 i/o 23l f2 i/o 22r f3 i/o 23r f4 v ddql g1 i/o 24r g2 i/o 24l g3 i/o 25l g4 v ddqr h1 i/o 26l h2 i/o 25r h3 i/o 26r h4 v ddqr j1 i/o 27l j2 i/o 28r j3 i/o 27r j4 v ddql k1 i/o 29r k2 i/o 29l k3 i/o 28l k4 v ddql l1 i/o 30l l2 i/o 31r l3 i/o 30r l4 v ddqr m1 i/o 32r m2 i/o 32l m3 i/o 31l m4 v ddqr n1 i/o 33l n2 i/o 34r n3 i/o 33r n4 v dd p1 i/o 35r p2 i/o 34l p3 tms p4 a 16r r1 i/o 35l r2 nc r3 trst r4 a 18r t1 nc t2 tck t3 nc t4 a 17r p5 a 13r r5 a 15r p12 a 6r p8 be 1r p9 be 0r r8 be 3r t8 be 2r p10 sem r t11 int r p11 busy r r12 a 4r t12 a 5r p13 a 3r p7 a 7r r13 a 1r t13 a 2r r6 a 12r t5 a 14r t14 a 0r r14 opt r p14 i/o 0l p15 i/o 0r r15 nc t15 nc t16 nc r16 nc p16 i/o 1l n16 i/o 2r n15 i/o 1r n14 i/o 2l m16 i/o 4l m15 i/o 3l m14 i/o 3r l16 i/o 5r l15 i/o 4r l14 i/o 5l k16 i/o 7l k15 i/o 6l k14 i/o 6r j16 i/o 8l j15 i/o 7r j14 i/o 8r h16 i/o 10r h15 io 9l h14 i/o 9r g16 i/o 11r g15 i/o 11l g14 i/o 10l f16 i/o 12l f14 i/o 12r f15 i/o 13r r9 ce 0r r11 v ss t6 a 11r t9 ce 1r a6 a 11l b10 r/ w l c13 a 3l p6 a 10r r10 r/ w r r7 a 9r t10 oe r t7 a 8r e5 v dd e6 v dd e7 v ss e8 v ss e9 v ss e10 v ss e11 v dd e12 v dd e13 v ddqr f5 v dd f6 nc f8 v ss f9 v ss f10 v ss f12 v dd f13 v ddqr g5 v ss g6 v ss g7 v ss g8 v ss g9 v ss g10 v ss g11 v ss g12 v ss g13 v ddql h5 v ss h6 v ss h7 v ss h8 v ss h9 v ss h10 v ss h11 v ss h12 v ss h13 v ddql j5 zz r j6 v ss j7 v ss j8 v ss j9 v ss j10 v ss j11 v ss j12 zz l j13 v ddqr k5 v ss k6 v ss k7 v ss k8 v ss l5 v dd l6 nc l7 v ss l8 v ss m5 v dd m6 v dd m7 v ss m8 v ss n5 v ddqr n6 v ddqr n7 v ddql n8 v ddql k9 v ss k10 v ss k11 v ss k12 v ss l9 v ss l10 v ss l11 v ss l12 v dd m9 v ss m10 v ss m11 v dd m12 v dd n9 v ddqr n10 v ddqr n11 v ddql n12 v ddql k13 v ddqr l13 v ddql m13 v ddql n13 v dd f7 v ss f11 v ss 5679 drw 02f
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 4 pin names notes: 1. v dd , opt x , and v ddqx must be set to appropriate operating levels prior to applying inputs on i/o x . 2. opt x selects the operating voltage levels for the i/os and controls on that port. if opt x is set to v dd (2.5v), then that port's i/os and controls will operate at 3.3v levels and v ddqx must be supplied at 3.3v. if opt x is set to v ss (0v), then that port's i/os and controls will operate at 2.5v levels and v ddqx must be supplied at 2.5v. the opt pins are independent of one another?both ports can operate at 3.3v levels, both can operate at 2.5v levels, or either can operate at 3.3v with the other at 2.5v. 3. the sleep mode pin shuts off all dynamic inputs, except jtag inputs, when asserted. optx, int x and the sleep mode pins themselves (zzx) are not affected during sleep mode. it is recommended that boundry scan not be operated during sleep mode. left port right port names ce 0l , ce 1l ce 0r , ce 1r chip enables (input) r/ w l r/ w r read/write enable (input) oe l oe r output enable (input) a 0l - a 18l a 0r - a 18r address (input) i/o 0l - i/o 35l i/o 0r - i/o 35r data input/output sem l sem r semaphore enable (input) int l int r interrupt flag (output) busy l busy r busy input be 0l - be 3l be 0r - be 3r byte enables (9-bit bytes) (input) v ddql v ddqr power (i/o bus) (3.3v or 2.5v) (1) (input) opt l opt r option for selecting v ddqx (1,2) (input) zz l zz r sleep mode pin (3) (input) v dd power (2.5v) (1) (input) v ss ground (0v) (input) tdi test data input tdo test data output tck test logic clock (10mhz) (input) tms test mode select (input) trst reset (initialize tap controller) (input) 5679 tbl 01
5 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. it is possible to read or write any combination of bytes during a given access. a few representative samples have been illust rated here. truth table i?read/write and enable control (1,2) oe sem ce 0 ce 1 be 3 be 2 be 1 be 0 r/ w zz byte 3 i/o 27-35 byte 2 i/o 18-26 byte 1 i/o 9-17 byte 0 i/o 0-8 mode xhhxxxxxxlhigh-zhigh-zhigh-zhigh-zdeselected?power down xhxlxxxxxlhigh-zhigh-zhigh-zhigh-zdeselected?power down xhl hhhhhxlhigh-zhigh-zhigh-zhigh-zall bytes deselected xhl hhhhl l lhigh-zhigh-zhigh-z d in write to byte 0 only x h l h h h l h l l high-z high-z d in high-z write to byte 1 only xhlhhlhhllhigh-z d in high-z high-z write to byte 2 only xhlhlhhhll d in high-z high-z high-z write to byte 3 only x h l h h h l l l l high-z high-z d in d in write to lower 2 bytes only xhlhllhhll d in d in high-z high-z write to upper 2 bytes only xhlhllllll d in d in d in d in write to all bytes l hl hhhhlhlhigh-zhigh-zhigh-z d out read byte 0 only lhlhhhlhhlhigh-zhigh-z d out high-z read byte 1 only lhlhhlhhhlhigh-z d out high-z high-z read byte 2 only lhlhlhhhhl d out high-z high-z high-z read byte 3 only l h l h h h l l h l high-z high-z d out d out read lower 2 bytes only lhlhllhhhl d out d out high-z high-z read upper 2 bytes only lhlhllllhl d out d out d out d out read all bytes hhlhllllxlhigh-zhigh-zhigh-zhigh-zoutputs disabled xxxxxxxxxhhigh-zhigh-zhigh-zhigh-zhigh-z sl eep mode 5679 tbl 02 truth table ii ? semaphore read/write control (1) notes: 1. there are eight semaphore flags written to i/o 0 and read from the i/os (i/o 0 -i/o 08 and i/o 18 -i/o 26 ). these eight semaphore flags are addressed by a 0 -a 2 . 2. ce = l occurs when ce 0 = v il and ce 1 = v ih . ce = h when ce 0 = v ih and/or ce 1 = v il . 3. each byte is controlled by the respective be n. to read data be n = v il . inputs (1) outputs mode ce (2) r/ w oe be 3 be 2 be 1 be 0 sem i/o 1-8, i/o 18-26 i/o 0 hhlx lx l ldata out data out read data in semaphore flag (3) h xxxxl l x data in write i/o 0 into semaphore flag lxxxxxx l ______ ______ not allowed 5679 tbl 03
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 6 recommended operating temperature and supply voltage (1) note: 1. this is the parameter ta. this is the "instant on" case temperature. grade ambient temperature gnd v dd commercial 0 o c to +70 o c0v2.5v + 100mv industrial -40 o c to +85 o c0v2.5v + 100mv 5679 tbl 04 notes: 1. these parameters are determined by device characterization, but are not production tested. 2. c out also references c i/o . capacitance (1) (t a = +25c, f = 1.0mh z ) pqfp only symbol parameter conditions max. unit c in input capacitance v in = 0v 15 pf c out (2) output capacitance v out = 0v 10.5 pf 5679 tbl 08 notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this is a steady-state dc parameter that applies after the power supply has reached its nominal operating value. power sequencing is not necessary; however, the voltage on any input or i/o pin cannot exceed v ddq during power supply ramp up. 3. ambient temperature under dc bias. no ac conditions. chip deselected. recommended dc operating conditions with v ddq at 2.5v symbol parameter min. typ. max. unit v dd core supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage (3) 2.4 2.5 2.6 v v ss ground 0 0 0 v v ih input high volltage (address, control & data i/o inputs) (3) 1.7 ____ v ddq + 100mv (2) v v ih input high voltage _ jtag 1.7 ____ v dd + 100mv (2) v v ih input high voltage - zz, op t v dd - 0.2v ____ v dd + 100mv (2) v v il input low voltage -0.3 (1) ____ 0.7 v v il input low voltage - zz, op t -0.3 (1) ____ 0.2 v 5679 tbl 05 notes: 1. v il (min.) = -1.0v for pulse width less than t rc /2 or 5ns, whichever is less. 2. v ih (max.) = v ddq + 1.0v for pulse width less than t rc /2 or 5ns, whichever is less. 3. to select operation at 2.5v levels on the i/os and controls of a given port, the opt pin for that port must be set to v ss (0v), and v ddqx for that port must be supplied as indicated above. absolute maximum ratings (1) symbol rating commercial & industrial unit v term (v dd ) v dd terminal voltage with respect to gnd -0.5 to 3.6 v v term (2) (v ddq ) v ddq terminal voltage with respect to gnd -0.3 to v ddq + 0.3 v v term (2) (inputs and i/o's) input and i/o terminal voltage with respect to gnd -0.3 to v ddq + 0.3 v t bias (3) temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn junction temperature +150 o c i out (for v ddq = 3.3v) dc output current 50 ma i out (for v ddq = 2.5v) dc output current 40 ma 5679 tbl 07 notes: 1. v il (min.) = -1.0v for pulse width less than t rc /2 or 5ns, whichever is less. 2. v ih (max.) = v ddq + 1.0v for pulse width less than t rc /2 or 5ns, whichever is less. 3. to select operation at 3.3v levels on the i/os and controls of a given port, the opt pin for that port must be set to v dd (2.5v), and v ddqx for that port must be supplied as indicated above. recommended dc operating conditions with v ddq at 3.3v symbol parameter min. typ. max. unit v dd core supply voltage 2.4 2.5 2.6 v v ddq i/o supply voltage (3) 3.15 3.3 3.45 v v ss ground 0 0 0 v v ih input high voltage (address, control &data i/o inputs) (3) 2.0 ____ v ddq + 150mv (2) v v ih input high voltage _ jtag 1.7 ____ v dd + 100mv (2) v v ih input high voltage - zz, op t v dd - 0.2v ____ v dd + 100mv (2) v v il input low voltage -0.3 (1) ____ 0.8 v v il input low voltage - zz, op t -0.3 (1) ____ 0.2 v 5679 tbl 06
7 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges dc electrical characteristics over the operating temperature and supply voltage range (v dd = 2.5v 100mv) notes: 1. v ddq is selectable (3.3v/2.5v) via opt pins. refer to page 6 for details. 2. applicable only for tms, tdi and trst inputs. 3. outputs tested in tri-state mode. dc electrical characteristics over the operating temperature and supply voltage range (3) (v dd = 2.5v 100mv) notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc , using "ac test conditions" at input levels of gnd to 3.3v. 2. f = 0 means no address or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, t a = 25c for typ, and are not production tested. i dd dc (f=0) = 200ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v ddqx - 0.2v ce x > v ddqx - 0.2v means ce 0x > v ddqx - 0.2v or ce 1x < 0.2v. "x" represents "l" for left port or "r" for right port. 6. i sb 1 , i sb 2 and i sb 4 will all reach full standby levels (i sb 3 ) on the appropriate port(s) if zz l and /or zz r = v ih . 70t653ms10 com'l only 70t653ms12 com'l & ind 70t653ms15 com'l only symbol parameter test condition version typ. (4) max. typ. (4) max. typ. (4) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled f = f max (1) com'l s 600 810 600 710 450 600 ma ind s ____ ____ 600 790 ____ ____ i sb1 (6) standby current (both ports - ttl level inputs) ce l = ce r = v ih f = f max (1) com'l s 180 240 150 210 120 170 ma ind s ____ ____ 150 260 ____ ____ i sb2 (6) standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f = f max (1) com'l s 400 530 360 460 300 400 ma ind s ____ ____ 360 510 ____ ____ i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v ddq - 0.2v, v in > v ddq - 0.2v or v in < 0.2v, f = 0 (2) com'ls420420420 ma ind s ____ ____ 440 ____ ____ i sb4 (6) full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v ddq - 0.2v (5) v in > v ddq - 0.2v or v in < 0.2v, active port, outputs disabled, f = f max (1) com'l s 400 530 460 300 400 ma ind s ____ ____ 360 510 ____ ____ i zz sleep mode current (both ports - ttl level inputs) zz l = zz r = v ih f = f max (1) com'ls420420420 ma ind s ____ ____ 440 ____ ____ 5679 tbl 10 symbol parameter test conditions 70t653m unit min. max. |i li | input leakage current (1) v ddq = max., v in = 0v to v ddq ___ 10 a |i li | jtag & zz input leakage current (1,2) v dd = max. , v in = 0v to v dd ___ + 60 a |i lo | output leakage current (1,3) ce 0 = v ih or ce 1 = v il , v out = 0v to v ddq ___ 10 a v ol (3.3v) output low voltage (1) i ol = +4ma, v ddq = min. ___ 0.4 v v oh (3.3v) output high voltage (1) i oh = -4ma, v ddq = min. 2.4 ___ v v ol (2.5v) output low voltage (1) i ol = +2ma, v ddq = min. ___ 0.4 v v oh (2.5v) output high voltage (1) i oh = -2ma, v ddq = min. 2.0 ___ v 5679 tbl 09
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 8 ac test conditions (v ddq - 3.3v/2.5v) input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v / gnd to 2.4v 2ns max. 1.5v/1.25v 1.5v/1.25v figure 1 5679 tbl 11 figure 1. ac output test load. 1.5v/1.25 50 ? 50 ? 5679 drw 03 10pf (tester) data out , 5679 drw 05 20 40 60 80 100 120 140 0 160 0 0.5 1 1.5 2 2.5 3 3.5 4 ? capacitance (pf) from ac test load ? t aa / t ace (typical, ns) figure 3. typical output derating (lumped capacitive load).
9 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges ac electrical characteristics over the operating temperature and supply voltage range (4) notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 1). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . either condition must be valid for the entire t ew time. ce = v il when ce 0 = v il and ce 1 = v ih . ce = v ih when ce 0 = v ih and/or ce 1 = v il . 4. these values are valid regardless of the power supply level selected for i/o and control signals (3.3v/2.5v). see page 6 for details. ac electrical characteristics over the operating temperature and supply voltage (4) symbol parameter 70t653ms10 com'l only 70t653ms12 com'l & ind 70t653ms15 com'l only unit min. max. min. max. min. max. read cycle t rc read cycle time 10 ____ 12 ____ 15 ____ ns t aa address access time ____ 10 ____ 12 ____ 15 ns t ace chip enable access time (3) ____ 10 ____ 12 ____ 15 ns t abe byte enable access time (3) ____ 5 ____ 6 ____ 7ns t aoe output enable access time ____ 5 ____ 6 ____ 7ns t oh output hold from address change 3 ____ 3 ____ 3 ____ ns t lz output low-z time chip enable and semaphore (1,2) 3 ____ 3 ____ 3 ____ ns t lzob output low-z time output enable and byte enable (1,2) 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,2) 040608ns t pu chip enable to power up time (2) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 8 ____ 8 ____ 12 ns t sop semaphore flag update pulse ( oe or sem ) ____ 4 ____ 6 ____ 8ns t saa semaphore address access time 2 10 2 12 2 15 ns t soe semaphore output enable access time ____ 5 ____ 6 ____ 7ns 5679 tbl 12 symbol parameter 70t653ms10 com'l only 70t653ms12 com'l & ind 70t653ms15 com'l only unit min. max. min. max. min. max. write cycle t wc write cycle time 10 ____ 12 ____ 15 ____ ns t ew chip enable to end-of-write (3) 7 ____ 9 ____ 12 ____ ns t aw address valid to end-of-write 7 ____ 9 ____ 12 ____ ns t as address set-up time (3) 0 ____ 0 ____ 0 ____ ns t wp write pulse width 7 ____ 9 ____ 12 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 5 ____ 7 ____ 10 ____ ns t dh data hold time 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 4 ____ 6 ____ 8ns t ow output active from end-of-write (1,2) 3 ____ 3 ____ 3 ____ ns t swrd sem flag write to read time 5 ____ 5 ____ 5 ____ ns t sps sem flag contention window 5 ____ 5 ____ 5 ____ ns 5679 tbl 13
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 10 timing of power-up power-down waveform of read cycles (4) notes: 1. timing depends on which signal is asserted last, oe , ce or be n. 2. timing depends on which signal is de-asserted first ce , oe or be n. 3. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa or t abe . 4. sem = v ih . 5. ce = l occurs when ce 0 = v il and ce 1 = v ih . ce = h when ce 0 = v ih and/or ce 1 = v il . t rc r/ w ce addr t aa oe be n 5679 drw 06 (3) t ace (3) t aoe (3) t abe (3) (1) t lz /t lzob t oh (2) t hz data out valid data (3) (5) . ce 5679 drw 07 t pu i cc i sb t pd 50% 50% .
11 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges timing waveform of write cycle no. 1, r/ w controlled timing (1,5,8) timing waveform of write cycle no. 2, ce controlled timing (1,5,8) notes: 1. r/ w or ce or be n = v ih during all address transitions for write cycles 1 and 2. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il, be n = v il , and a r/ w = v il for memory array writing cycle. 3. t wr is measured from the earlier of ce , be n or r/ w (or sem or r/ w ) going high to the end of write cycle. 4. during this period, the i/o pins are in the output state and input signals must not be applied. 5. if the ce or sem = v il transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal is asserted last, ce or r/ w . 7. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from steady state with the output test load (figure 1). 8. if oe = v il during r /w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off and data to be placed on the bus for the required t dw . if oe = v ih during an r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 9. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . t ew must be met for either condition. ce = v il when ce 0 = v il and ce 1 = v ih . ce = v ih when ce 0 = v ih and/or ce 1 = v il . r/ w t wc t hz t aw t wr t as t wp data out (2) t wz t dw t dh t ow oe address data in ce or sem (9) (6) (4) (4) (3) 5679 drw 10 (7) (7) t lz , t hz (7) (7) be n (9) 5679 drw 11 t wc t as t wr t dw t dh address data in r/ w t aw t ew be n (3) (2) (6) ce or sem (9) (9) . .
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 12 unlike other vendors' asynchronous random access memories, the idt70t653m is capable of performing multiple back-to-back write operations without having to pulse the r/ w , ce , or be n signals high during address transitions. this rapidwrite mode functionality allows the system designer to achieve optimum back-to-back write cycle performance without the difficult task of generating narrow reset pulses every cycle, simplifying system design and reducing time to market. during this new rapidwrite mode, the end of the write cycle is now defined by the ending address transition, instead of the r/ w or ce or be n transition to the inactive state. r/ w , ce , and be n can be held active throughout the address transition between write cycles. care must be taken to still meet the write cycle time (t wc ), the time in which the address inputs must be stable. input data setup and hold times (t dw and t dh ) will now be referenced to the ending address transition. in this rapidwrite mode the i/o will remain in the input mode for the duration of the operations due to r/ w being held low. all standard write cycle specifications must be adhered to. however, t as and t wr are only applicable when switching between read and write operations. also, there are two additional conditions on the address inputs that must also be met to ensure correct address controlled writes. these specifications, the allowable address skew (t aas ) and the address rise/fall time (t arf ), must be met to use the rapidwrite mode. if these conditions are not met there is the potential for inadvertent write operations at random intermediate locations as the device transitions between the desired write addresses. 5679 drw 08 t wc t wc t wc t ew t wp t wz t dh t dw t dw t dw t ow t wr address ce or sem (6) be n r/ w data in data out (2) (5) (5) t dh t dh (4) timing waveform of write cycle no. 3, rapidwrite mode write cycle (1,3) notes: 1. oe = v il for this timing waveform as shown. oe may equal v ih with same write functionality; i/o would then always be in high-z state. 2. a write occurs during the overlap (t ew or t wp ) of a ce = v il, be n = v il , and a r/ w = v il for memory array writing cycle. the last transition low of ce , be n, and r/ w initiates the write sequence. the first transition high of ce , be n, and r/ w terminates the write sequence. 3. if the ce or sem = v il transition occurs simultaneously with or after the r/ w = v il transition, the outputs remain in the high-impedance state. 4. the timing represented in this cycle can be repeated multiple times to execute sequential rapidwrite mode writes. 5. this parameter is guaranteed by device characterization, but is not production tested. transition is measured 0mv from steady state with the output test load (figure 1). 6. to access ram, ce = v il and sem = v ih . to access semaphore, ce = v ih and sem = v il . t ew must be met for either condition. ce = v il when ce 0 = v il and ce 1 = v ih . ce = v ih when ce 0 = v ih and/or ce 1 = v il . rapidwrite mode write cycle
13 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges ac electrical characteristics over the operating temperature range and supply voltage range for rapidwrite mode write cycle (1) symbol parameter min max unit t aas allowable address skew for rapidwrite mode ____ 1ns t arf address rise/fall time for rapidwrite mode 1.5 ____ v/ns 5679 tbl 14 note: 1. timing applies to all speed grades when utilizing the rapidwrite mode write cycle. timing waveform of address inputs for rapidwrite mode write cycle 5679 drw 09 a 0 a 18 t aas t arf t arf
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 14 timing waveform of semaphore read after write timing, either side (1) notes: 1. d or = d ol = v il , ce l = ce r = v ih . refer to truth table ii for appropriate be controls. 2. all timing is the same for left and right ports. port "a" may be either left or right port. "b" is the opposite from port "a" . 3. this parameter is measured from r/ w "a" or sem "a" going high to r/ w "b" or sem "b" going high. 4. if t sps is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be gra nted the semaphore flag. timing waveform of semaphore write contention (1,3,4) notes: 1. ce 0 = v ih and ce 1 = v il are required for the duration of both the write cycle and the read cycle waveforms shown above. refer to truth table ii for de tails and for appropriate be n controls. 2. "data out valid" represents all i/o's (i/o 0 - i/o 8 and i/o 18 - i/o 26 ) equal to the semaphore value. sem (1) 5679 drw 12 t aw t ew i/o valid address t saa r/ w t wr t oh t ace valid address data valid in data out t dw t wp t dh t as t swrd t soe read cycle write cycle a 0 -a 2 oe valid (2) t sop t sop . sem "a" 5679 drw 13 t sps match r/ w "a" match a 0"a" -a 2"a" side "a" (2) sem "b" r/ w "b" a 0"b" -a 2"b" side "b" (2) .
15 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges notes: 1. port-to-port delay through ram cells from writing port to reading port, refer to timing waveform of write with port-to-port r ead. 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of the max. spec, t wdd ? t wp (actual), or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited on port "b" during contention on port "a". 5. to ensure that a write cycle is completed on port "b" after contention on port "a". ac electrical characteristics over the operating temperature and supply voltage range symbol parameter 70t653ms10 com'l only 70t653ms12 com'l & ind 70t653ms15 com'l only unit min. max. min. max. min. max. busy timing t wb busy input to write (4) 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (5) 7 ____ 9 ____ 12 ____ ns port-to-port delay timing t wdd write pulse to data delay (1) ____ 14 ____ 16 ____ 20 ns t ddd write data valid to read data delay (1) ____ 14 ____ 16 ____ 20 ns 5679 tbl 15 symbol parameter 70t65m3s10 com'l only 70t653ms12 com'l & ind 70t6539ms15 com'l only min. max. min. max. min. max. sleep mode timing (zzx=v ih ) t zzs sleep mode set time 10 ____ 12 ____ 15 ____ t zzr sleep mode reset time 10 ____ 12 ____ 15 ____ t zzpd sleep mode power down time (4) 10 ____ 12 ____ 15 ____ t zzpu sleep mode power up time (4) ____ 0 ____ 0 ____ 0 5679 tbl 15a ac electrical characteristics over the operating temperature and supply voltage range (1,2,3) notes: 1. timing is the same for both ports. 2. the sleep mode pin shuts off all dynamic inputs, except jtag inputs, when asserted. optx, int x and the sleep mode pins themselves (zzx) are not affected during sleep mode. it is recommended that boundary scan not be operated during sleep mode. 3. these values are valid regardless of the power supply level selected for i/o and control signals (3.3v/2.5v). see page 6 for details. 4. this parameter is guaranteed by device characterization, but is not production tested.
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 16 timing waveform of write with busy notes: 1. t wh must be met for busy input. 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 5679 drw 15 r/ w "a" busy "b" t wb r/ w "b" t wh (1) (2) t wp . 5679 drw 14a t dw addr "a" t wc data out "b" match t wp r/ w "a" data in "a" addr "b" t dh valid match r/ w "b" valid t ddd (3) t wdd . (4) ac electrical characteristics over the operating temperature and supply voltage range (1,2) 70t653ms10 com'l only 70t653ms12 com'l & ind 70t653ms15 com'l only symbol parameter min.max.min.max.min.max.unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 10 ____ 12 ____ 15 ns t inr interrupt reset time ____ 10 ____ 12 ____ 15 ns 5679 tbl 16 notes: 1. timing is the same for both ports. 2. these values are valid regardless of the power supply level selected for i/o and control signals (3.3v/2.5v). see page 6 for details. timing waveform of write with port-to-port read (1,3) notes: 1. ce 0l = ce 0r = v il ; ce 1l = ce 1r = v ih . 2. oe = v il for the reading port. 3. all timing is the same for left and right ports. port "a" may be either the left or right port. port "b" is the port opposite from port "a". 4. r/ w b = v ih .
17 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges truth table iii ? interrupt flag (1,4) waveform of interrupt timing (1) notes: 1. all timing is the same for left and right ports. port ?a? may be either the left or right port. port ?b? is the port opposite from port ?a?. 2. refer to interrupt truth table. 3. ce x = v il means ce 0 x = v il and ce 1 x = v ih . ce x = v ih means ce 0 x = v ih and/or ce 1 x = v il . 4. timing depends on which enable signal ( ce or r/ w ) is asserted last. 5. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. notes: 1. assumes busy l = busy r =v ih . ce 0 x = v il and ce 1 x = v ih . 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. int l and int r must be initialized at power-up. 5679 drw 18 addr "a" interrupt set address ce "a" (3) r/ w "a" t as t wc t wr (4) (5) t ins (4) int "b" (2) . 5679 drw 19 addr "b" interrupt clear address ce "b" (3) oe "b" t as t rc (4) t inr (4) int "b" (2) . left port right port function r/ w l ce l oe l a 18l -a 0l int l r/ w r ce r oe r a 18r -a 0r int r llx7ffffxxxx x l (2) set right int r flag x x x x x x l l 7ffff h (3) reset right int r flag xxx x l (3) l l x 7fffe x set left int l flag x l l 7fffe h (2) x x x x x reset left int l flag 5679 tbl 17
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 18 semaphore flags. these flags allow either processor on the left or right side of the dual-port ram to claim a privilege over the other processor for functions defined by the system designer?s software. as an example, the semaphore can be used by one processor to inhibit the other from accessing a portion of the dual-port ram or any other shared resource. the dual-port ram features a fast access time, with both ports being completely independent of each other. this means that the activity on the left port in no way slows the access time of the right port. both ports are identical in function to standard cmos static ram and can be read from or written to at the same time with the only possible conflict arising from the simultaneous writing of, or a simultaneous read/write of, a non- semaphore location. semaphores are protected against such ambiguous situations and may be used by the system program to avoid any conflicts in the non-semaphore portion of the dual-port ram. these devices have an automatic power-down feature controlled by ce 0 and ce 1 , the dual- port ram chip enables, and sem , the semaphore enable. the ce 0 , ce 1 , and sem pins control on-chip power down circuitry that permits the respective port to go into standby mode when not selected. systems which can best use the idt70t653m contain multiple processors or controllers and are typically very high-speed systems which are software controlled or software intensive. these ystems can benefit from a performance increase offered by the idt70t653ms hardware semaphores, which provide a lockout mechanism without requiring complex programming. software handshaking between processors offers the maximum in system flexibility by permitting shared resources to be allocated invarying configurations. the idt70t653m does not use its semaphore flags to control any resources through hardware, thus allowing the system designer total flexibility in system architecture. an advantage of using semaphores rather than the more common methods of hardware arbitration is that wait states are never incurred in either processor. this can prove to be a major advantage in very high-speed systems. functional description the idt70t653m provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt70t653m has an automatic power down feature controlled by ce . the ce 0 and ce 1 control the on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = high). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 7fffe (hex), where a write is defined as ce r = r/ w r = v il per the truth table. the left port clears the interrupt through access of address location 7fffe when ce l = oe l = v il , r/ w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 7ffff (hex) and to clear the interrupt flag ( int r ), the right port must read the memory location 7ffff. the message (36 bits) at 7fffe or 7ffff is user-defined since it is an addressable sram location. if the interrupt function is not used, address locations 7fffe and 7ffff are not used as mail boxes, but as part of the random access memory. refer to truth table iii for the interrupt operation. busy logic the busy pin operates as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. semaphores the idt70t653m is an extremely fast dual-port 512k x 36 cmos static ram with an additional 8 address locations dedicated to binary truth table iv ? example of semaphore procurement sequence (1,2,3) notes: 1. this table denotes a sequence of events for only one of the eight semaphores on the idt70t653m. 2. there are eight semaphore flags written to via i/o 0 and read from i/os (i/o 0 -i/o 8 and i/o 18 -i/o 26 ). these eight semaphores are addressed by a 0 - a 2 . 3. ce = v ih , sem = v il to access the semaphores. refer to the semaphore read/write control truth table. functions d 0 - d 8 left d 18 - d 26 left d 0 - d 8 right d 18 - d 26 right status no action 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token right port writes "0" to semaphore 0 1 no change. right side has no write access to semaphore left port writes "1" to semaphore 1 0 right port obtains semaphore token left port writes "0" to semaphore 1 0 no change. left port has no write access to semaphore right port writes "1" to semaphore 0 1 left port obtains semaphore token left port writes "1" to semaphore 1 1 semaphore free right port writes "0" to semaphore 1 0 right port has semaphore token right port writes "1" to semaphore 1 1 semaphore free left port writes "0" to semaphore 0 1 left port has semaphore token left port writes "1" to semaphore 1 1 semaphore free 5679 tbl 19
19 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges verifies its success in setting the latch by reading it. if it was successful, it proceeds to assume control over the shared resource. if it was not successful in setting the latch, it determines that the right side processor has set the latch first, has the token and is using the shared resource. the left processor can then either repeatedly request that semaphore?s status or remove its request for that semaphore to perform another task and occasionally attempt again to gain control of the token via the set and test sequence. once the right side has relinquished the token, the left side should succeed in gaining control. the semaphore flags are active low. a token is requested by writing a zero into a semaphore latch and is released when the same side writes a one to that latch. the eight semaphore flags reside within the idt70t653m in a separate memory space from the dual-port ram. this address space is accessed by placing a low input on the sem pin (which acts as a chip select for the semaphore flags) and using the other control pins (address, ce 0 , ce 1 ,r/ w and be n) as they would be used in accessing a standard static ram. each of the flags has a unique address which can be accessed by either side through address pins a 0 ? a 2 . when accessing the semaphores, none of the other address pins has any effect. when writing to a semaphore, only data pin d 0 is used. if a low level is written into an unused semaphore location, that flag will be set to a zero on that side and a one on the other side (see truth table iv). that semaphore can now only be modified by the side showing the zero. when a one is written into the same location from the same side, the flag will be set to a one for both sides (unless a semaphore request from the other side is pending) and then can be written to by both sides. the fact that the side which is able to write a zero into a semaphore subsequently locks out writes from the other side is what makes semaphore flags useful in interprocessor communications. (a thorough discussion on the use of this feature follows shortly.) a zero written into the same location from the other side will be stored in the semaphore request latch for that side until the semaphore is freed by the first side. when a semaphore flag is read, its value is spread into all data bits so that a flag that is a one reads as a one in all data bits and a flag containing a zero reads as all zeros for a semaphore read, the sem , be n, and oe signals need to be active. (please refer to truth table ii). furthermore, the read value is latched into one side?s output register when that side's semaphore select ( sem , be n) and output enable ( oe ) signals go active. this serves to disallow the semaphore from changing state in the middle of a read cycle due to a write cycle from the other side. a sequence write/read must be used by the semaphore in order to guarantee that no system level contention will occur. a processor requests access to shared resources by attempting to write a zero into a semaphore location. if the semaphore is already in use, the semaphore request latch will contain a zero, yet the semaphore flag will appear as one, a fact which the processor will verify by the subsequent read (see table iv). as an example, assume a processor writes a zero to the left port at a free semaphore location. on a subsequent read, the processor will verify that it has written success- fully to that location and will assume control over the resource in question. meanwhile, if a processor on the right side attempts to write a zero to the same semaphore flag it will fail, as will be verified by the fact that a one will be read from that semaphore on the right side during subsequent read. had a sequence of read/write been used instead, system contention problems could have occurred during the gap between the read and write cycles. it is important to note that a failed semaphore request must be followed by either repeated reads or by writing a one into the same location. the reason for this is easily understood by looking at the simple logic diagram of the semaphore flag in figure 4. two semaphore request latches feed into a semaphore flag. whichever latch is first to present a zero to the semaphore flag will force its side of the semaphore flag low and the other side high. this condition will continue until a one is written to the same semaphore request latch. if the opposite side semaphore request latch has been written to zero in the meantime, the semaphore flag will flip over to the other side as soon as a one is written into the first request latch. the opposite side flag will now stay low until its semaphore request latch is written to a one. from this it is easy to understand that, if a semaphore is requested and the processor which requested it no longer needs the resource, the entire system can hang up until a one is written into that semaphore request latch. the critical case of semaphore timing is when both sides request a single token by attempting to write a zero into it at the same time. the semaphore logic is specially designed to resolve this problem. if simulta- neous requests are made, the logic guarantees that only one side receives the token. if one side is earlier than the other in making the request, the first side to make the request will receive the token. if both requests arrive at the same time, the assignment will be arbitrarily made to one port or the other. one caution that should be noted when using semaphores is that semaphores alone do not guarantee that access to a resource is secure. as with any powerful programming technique, if semaphores are misused or misinterpreted, a software error can easily happen. initialization of the semaphores is not automatic and must be handled via the initialization program at power-up. since any semaphore request flag which contains a zero must be reset to a one, all semaphores on both sides should have a one written into them at initialization from both sides to assure that they will be free when needed. figure 4. idt70t653m semaphore logic d 5679 drw 21 0 d q write d 0 d q write semaphore request flip flop semaphore request flip flop lport rport semaphore read semaphore read how the semaphore flags work the semaphore logic is a set of eight latches which are indepen- dent of the dual-port ram. these latches can be used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. the semaphores provide a hardware assist for a use assignment method called ?token passing allocation.? in this method, the state of a semaphore latch is used as a token indicating that a shared resource is in use. if the left processor wants to use this resource, it requests the token by setting the latch. this processor then
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 20 timing waveform of sleep mode (1,2) notes: 1. ce 1 = v ih. 2. all timing is same for left and right ports. i z z i d d 5 6 7 9 d r w 2 2 , z z t z z p d c e 0 d a t a v a l i d a d d r e s s t z z r n o n e w r e a d s o r w r i t e s a l l o w e d n o r m a l o p e r a t i o n n o r m a l o p e r a t i o n s l e e p m o d e n o r e a d s o r w r i t e s a l l o w e d v a l i d d a t a a d d r e s s t z z s t z z p u
21 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges sleep mode the idt70t653m is equipped with an optional sleep or low power mode on both ports. the sleep mode pin on both ports is active high. during normal operation, the zz pin is pulled low. when zz is pulled high, the port will enter sleep mode where it will meet lowest possible power conditions. the sleep mode timing diagram shows the modes of operation: normal operation, no read/write allowed and sleep mode. for a period of time prior to sleep mode and after recovering from sleep mode (t zzs and t zzr ), new reads or writes are not allowed. if a write or read operation occurs during these periods, the memory array may be corrupted. validity of data out from the ram cannot be guaranteed immediately after zz is asserted (prior to being in sleep). during sleep mode the ram automatically deselects itself. the ram disconnects its internal buffer. all outputs will remain in high-z state while in sleep mode. all inputs are allowed to toggle. the ram will not be selected and will not perform any reads or writes. jtag functionality and configuration the idt70t653m is composed of two independent memory arrays, and thus cannot be treated as a single jtag device in the scan chain. the two arrays (a and b) each have identical characteristics and commands but must be treated as separate entities in jtag operations. please refer to figure 5. jtag signaling must be provided serially to each array and utilizes the information provided in the identification register definitions, scan register sizes, and system interface parameter tables. specifically, commands for array b must precede those for array a in any jtag operations sent to the idt70t653m. please reference application note an-411, "jtag testing of multichip modules" for specific instructions on performing jtag testing on the idt70t653m. an-411 is available at www.idt.com. array a array b tck tms trst tdi tdoa tdib tdo 5679 drw 23 idt70t653m figure 5. jtag configuration for idt70t653m
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 22 jtag ac electrical characteristics (1,2,3,4,5) 70t653m symbol parameter min. max. units t jcyc jtag clock input period 100 ____ ns t jch jtag clock high 40 ____ ns t jcl jtag clock low 40 ____ ns t jr jtag clock rise time ____ 3 (1) ns t jf jtag clock fall time ____ 3 (1) ns t jrst jtag reset 50 ____ ns t jrsr jtag reset recovery 50 ____ ns t jcd jtag data output ____ 25 ns t jdc jtag data output hold 0 ____ ns t js jtag setup 15 ____ ns t jh jtag hold 15 ____ ns 5679 tbl 20 notes: 1. guaranteed by design. 2. 30pf loading on external output signals. 3. refer to ac electrical test conditions stated earlier in this document. 4. jtag operations occur at one speed (10mhz). the base device may run at any speed specified in this datasheet. 5. jtag cannot be tested in sleep mode. jtag timing specifications tck device inputs (1) / tdi/tms device outputs (2) / tdo trst t jcd t jdc t jrst t js t jh t jcyc t jrsr t jf t jcl t jr t jch 5679 drw 24 x notes: 1. device inputs = all device inputs except tdi, tms, tck and trst . 2. device outputs = all device outputs except tdo.
23 idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges identification register definitions instruction field array b value array b instruction field array a value array a description revision number (31:28) 0x0 revision number (63:60) 0x0 reserved for version number idt device id (27:12) 0x33b idt device id (59:44) 0x33b defines idt part number idt jedec id (11:1) 0x33 idt jedec id (43:33) 0x33 allows unique identification of device vendor as idt id register indicator bit (bit 0) 1 id register indicator bit (bit 32) 1 indicates the presence of an id register 5679 tbl 21 scan register sizes register name bit size array a bit size array b bit size 70t653m instruction (ir) 4 4 8 bypass (byr) 1 1 2 identification (idr) 32 32 64 boundary scan (bsr) note (3) note (3) note (3) 5679 tbl 22 system interface parameters instruction code description extest 00000000 forces contents of the boundary scan cells onto the device outputs (1) . places the boundary scan register (bsr) between tdi and tdo. b ypas s 11111111 p lac e s the b y p as s re g is te r (byr) b e twe e n tdi and tdo. idcode 00100010 loads the id register (idr) with the vendor id code and places the register between tdi and tdo. highz 01000100 places the bypass register (byr) between tdi and tdo. forces all device output drivers to a high-z state. clamp 00110011 uses byr. forces contents of the boundary scan cells onto the device outputs. places the bypass register (byr) between tdi and tdo. sample/preload 00010001 places the boundary scan register (bsr) between tdi and tdo. sample allows data from device inputs (2) and outputs (1) to be captured in the boundary scan cells and shifted serially through tdo. preload allows data to be input serially into the boundary scan cells via the tdi. reserved all other codes several combinations are reserved. do not use codes other than those identified above. 5679 tbl 23 notes: 1. device outputs = all device outputs except tdo. 2. device inputs = all device inputs except tdi, tms, tck and trst . 3. the boundary scan descriptive language (bsdl) file for this device is available on the idt website (www.idt.com), or by conta cting your local idt sales representative.
idt70t653m high-speed 2.5v 512k x 36 asynchronous dual-port static ram industrial and commercial temperature ranges 24 ordering information a 999 a a i (1) standard power 18mbit (512k x 36) asynchronous dual-port ram 256-ball bga (bc-256) 5679 drw 25 commercial only commercial & industrial commercial only s 70t653m bc 10 12 15 device type power speed package process/ temperature range blank commercial (0 c to +70 c) industrial (-40 c to +85 c) speed in nanoseconds a g (2) green a 8 blank tube or tray tape and reel xxxxx the idt logo is a registered trademark of integrated device technology, inc. datasheet document history: 10/08/03: initial datasheet 10/20/03: page 1 added "includes jtag functionality" to features page 13 corrected t arf to 1.5v/ns min 09/28/04: removed "preliminary" status page 11 updated timing waveform of write cycle no. 1, r /w controlled timing page 21 added jtag configuration and jtag functionality descriptions page 1 & 24 replaced old ? logo with the new tm logo 06/30/05: page 1 added green availability to features page 24 added green indicator to ordering information 07/25/08: page 7 corrected a typo in the dc chars table 01/19/09: page 24 removed "idt" from orderable part number 06/15//15: page 3 removed the date from the bc256 pin configuration page 24 added tape and reel indicators and added footnote annotations to the ordering information corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com note: 1. contact your local sales office for industrial temp range for other speeds, packages and powers. 2. green parts available. for specific speeds, packages and powers contact your local sales office . ?

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